Luc Van den hove, Executive Vice President & COO, IMEC
Last Updated: July 1, 2008: 5:52 PM CST
Starting on a positive note, I am confident that the atmosphere at SEMICON West will be upbeat despite the fact that the outlook for the semiconductor industry at the beginning of 2008 was rather gloomy. Our sector is now in a more mature phase, and we cannot always count on a double-digit growth. Moreover, I would not be surprised if the second half of the year turns out to be considerably better.
Having said that, in which areas do I look for action and announcements at SEMICON West?
Intel, Samsung and TSMC recently agreed to cooperate on a transition to 450 mm wafer production, beginning in 2012. I expect, therefore, that there will be a lot of buzz around 450 mm, testifying to the upbeat atmosphere and positive outlook in the industry.
The semiconductor industry is currently taking some important hurdles toward further scaling. I hope to hear some news about improvements and optimizations in those areas.
First, there is extreme ultraviolet (EUV) lithography. Recently, major progress was announced; two fully functioning systems have produced the first devices. Of course, it will take another few years before EUV can be taken into production. In the meantime, for those applications that need extreme scaling and the smallest possible pitch, there is only one solution: double patterning (DP). What we need to see now are simple, cost-friendly techniques that make DP more easily applicable. Examples are spacer lithography or techniques allowing DP with only one etch step.
A second critical area concerns improvements and optimizations of high-k/metal gate, which is needed to implement this technology at the 32 nm node. Here also, the industry is hoping to see more cost-friendly solutions, especially for implementation in foundry processes and for the use of high-k in
cost-sensitive DRAM processes.
In the area of packaging, the industry is working on 3-D integration and suitable 3-D design methods. For technological solutions, the direction is toward smaller, denser interconnects and vias, moving toward 3-D stacked ICs. There are many options, and I would expect to see some initiatives toward standardization. Apart for the technological challenges, the IC design will have to follow suit to make the most of the 3-D possibilities that are opening up.
And, of course, there is a lot of action going on in photovoltaics, so we'll probably see some interesting evolutions there, too.
